1. Field of the Invention
The present invention generally relates to phase-locked loops (PLL) used for zone bit recording in hard disk systems, for example, and more particularly to improvement of the voltage-controlled oscillator (VCO) portion of the phase-locked loop.
2. Related Technical Art
Currently, phase-locked loops widely used in magnetic disk devices and other types of data separators comprise a first phase-locked loop operating in synchronization with a data pulse and a second phase-locked loop operating in synchronization with a reference clock, as disclosed in Japanese Laid-Open Patent Publication 59-28209, which was configured to be locked in at a high speed or quickly regardless of whether the data transfer rate changed. This type of phase-locked loop had a configuration as shown in FIG. 4. That is, a first phase-locked loop 10 used a phase comparator (PC) 12 to compare the phases of a data pulse string S.sub.IN and an oscillator output V.sub.1, and outputs a phase difference detection signal, a charge pump 14 that provides current to be charged and discharged to a loop filter 16, acting as a low-pass filter (LPF), in a subsequent stage based on the phase difference detection signal, and a voltage-controlled oscillator (VCO1) 18 in which an oscillation frequency f.sub.OS1 was controlled by a control voltage V.sub.F1, output by loop filter 16. A second phase-locked loop 20 used a phase comparator (PC) 22 to compare the phases of a reference clock CLK and an oscillator output V.sub.2 and output a phase detection signal. A charge pump 24 that provides the current to be charged and discharged to the loop filter 26, acting as a low-pass filter (LPF), in a subsequent stage based on the second phase detection signal, and a voltage-controlled oscillator (VCO2) 28 in which an oscillation frequency f.sub.OS2 was controlled in responce to a control voltage V.sub.F2, output by loop filter 16, were also used. The voltage-controlled oscillators 18 and 28 are each circuits with characteristic constants equal to each other, and each has a control input terminal a and an offset voltage (reference voltage) terminal b. Output V.sub.F1 of loop filter 16 and output V.sub.F2 of loop filter 26 of second phase-locked loop 20 are impressed on control input terminal a and offset voltage (reference voltage) terminal b, respectively, of voltage-controlled oscillator 18 of first phase-locked loop 10. An intermediate voltage V.sub.DD /2 (DC voltage) of a power source voltage V.sub.DD and output V.sub.F2 of loop filter 26 are impressed on control input terminal a and offset voltage terminal b, respectively, of voltage-controlled oscillator 28 of second phase-locked loop 20. Voltage-controlled oscillators 18 and 28 each use, as shown in FIG. 5, a voltage-current converter (V/I) 32 and a current frequency converter (I/F) 34. Voltage-current converter 32 comprises a parallel current path made using a MOS transistor Tr.sub.1 which is current-controlled by the voltage impressed on control input terminal a and a MOS transistor Tr.sub.2 which is current-controlled by the voltage impressed on offset voltage terminal b, a load MOS transistor Tr.sub.3 connected in series with this parallel current path, an output transistor Tr.sub.4, which acts as a current mirror circuit and uses load MOS transistor Tr.sub.3 as its input transistor, and a load MOS transistor Tr.sub.5 connected in series to transistor Tr.sub.4. Current frequency converter (I/F) 34 is a commonly used ring oscillator having three stages of inverters designated here as INV.sub.1 -INV.sub.3.
In only the first phase-locked loop 10, locking occurs when input of a data pulse string starts, and a considerable amount of time is required until control voltage V.sub.F1, output by loop filter 16, reaches approximately V.sub.DD /2, but by adding a reference clock CLK to second phase-locked loop 20 in advance to preset it to a locked condition and supplying output V.sub.F2 of loop filter 26 to offset voltage terminal b of voltage-controlled oscillator 18 in first phase-locked loop 10, first phase-locked loop 10 is locked in at high speed regardless of whether the data transfer rate changes.
However, phase-locked loops having the above configuration present the following problems.
(1) If control voltage V.sub.F1, output by loop filter 16 in first phase-locked loop 10, is V.sub.DD /2 (locked condition of first phase-locked loop 10), the added current (combined current) I of the current (control current) I.sub.1 controlled by control voltage V.sub.F1 and flowing to transistor Tr.sub.1, and the current (offset current) I.sub.2 controlled by offset voltage V.sub.F2 and flowing to transistor Tr.sub.2 are generated, and a current proportioned to added current I is supplied to current frequency converter 34. That is, an oscillation frequency f.sub.OS1 of voltage-controlled oscillator 18 is determined by the sum of control current I.sub.1 and offset current I.sub.2. Since control voltage V.sub.F1 oscillates up and down with one-half the power source voltage V.sub.DD as a reference, the center frequency is determined by the sum of control current I.sub.1, as determined by V.sub.DD /2, and offset current I.sub.2, even when there is no phase difference (locked condition). Therefore, the band of the center frequency expands very much even when the offset voltage is changed. This is due to the fact that even when the offset current is narrowed down in order to lower the center frequency, control current I.sub.1, as determined by V.sub.DD /2 in a locked condition, is already flowing.
In zone bit recording in hard disk systems, etc., a data pulse string S.sub.IN is generated at data transfer rates of four zones (f.sub.1 =8 MHz, f.sub.2 =10 MHz, f.sub.3 =12 MHz, f.sub.4 =14 MHz) and the data transfer rate is changed by switching among these four rates. Phase-locked loops such as that described above cannot be applied to systems requiring a wide range of data transfer rates such as this. This is due to the fact that the band width of the center frequency is too narrow, and it is not a control system that can freely vary the center frequency. Therefore, a phase-locked loop that can follow a wide range of data transfer rates for a data pulse string has been desired.
(2) Generally, when the loop filter is a lag-lead filter comprising a series circuit made up of a resistance R and a capacitor C, the following two equations are extremely important as equations that describe the basic characteristics of the phase-locked loop. EQU .omega..sub.n =(K.sub.v .multidot.K.sub.c /C).sup.1/2 ( 1) EQU .xi.=CR.omega..sub.n /2 (2)
where, .omega..sub.n is the natural frequency (characteristic frequency), .xi. is the damping coefficient (damping factor), K.sub.v is a voltage frequency conversion coefficient of the voltage-controlled oscillator, and K.sub.c is a conversion coefficient including the phase comparator and the charge pump. When a phase-locked loop is applied to a data separator circuit of a magnetic storage device, etc., it is necessary to change the natural frequency .omega..sub.n in proportion to the data transfer rate when the data transfer rate changes. The damping coefficient .xi., on the other hand, must remain a fixed value regardless of the data transfer rate. This is important from the standpoint of the phase step response and peak shift margin characteristic of the phase-locked loop. Therefore, when the data transfer rate is low (when the center frequency is low), the voltage frequency conversion coefficient K.sub.v of the voltage-controlled oscillator 18 must be lowered, and when the data transfer rate is high (when the center frequency is high), the voltage frequency conversion coefficient K.sub.v must be raised. However, in the voltage-controlled oscillators 18 and 28 of the above phase-locked loop, the voltage frequency conversion coefficient K.sub.v is fixed due to the physical dimensional ratio of transistor Tr.sub.1 for the control current and transistor Tr.sub.2 for the offset current, and, therefore, the voltage frequency conversion coefficient K.sub.v cannot be linked to the data transfer rate.
(3) Since the above phase-locked loop is locked into high speed when input of the data pulse string starts, a configuration is employed that adds a second phase-locked loop 20, whereby, if control input voltage V.sub.F1 of voltage-controlled oscillator 18 of first phase-locked loop 10 is equal to control input voltage V.sub.DD /2 of voltage-controlled oscillator 28 of second phase-locked loop 20, the oscillation frequencies become equal to each other.
In zone bit recording, the frequency of the reference clock CLK input to phase comparator 22 of second phase-locked loop 20 must be changed according to the corresponding data transfer rate, in which case, the oscillation frequency of voltage-controlled oscillator 28 is synchronized to the frequency of reference clock CLK, and output voltage V.sub.F2 of loop filter 26, i.e., value of the offset input voltage of voltage-controlled oscillator 18, becomes different from previous zones. However, as shown in FIG. 6, offset input voltage V.sub.F2 has a waveform that superposes an AC voltage component (pulse) V.sub.C corresponding to the charge-discharge period on the DC voltage component V.sub.D corresponding to an integrating action of the loop filter, and, therefore, DC voltage component V.sub.D cannot be freely changed without restriction over the entire range (0-V.sub.DD) of the power source voltage. This is because since AC voltage component (pulse) V.sub.C generated by the charging and discharging of charge pump 24 corresponds to the phase difference detection signal, when DC voltage component V.sub.D approaches V.sub.DD or V.sub.SS (ground potential), which are far removed from V.sub.DD /2, the AC voltage component (pulse) V.sub.C is clipped at a top or bottom limit and the control information for phase locking is corrupted. Therefore, the area of change for DC component V.sub.D of the output of loop filter 26 is limited to a neighborhood range extending above and below the reference V.sub.DD /2, and for this reason it is impossible to accommodate a wide range of data transfer rates.
Furthermore, the output of loop filter 26 is not only used to accommodate differing data transfer rates, it is also supplied to offset input b of voltage-controlled oscillator 18 to compensate for fluctuations in the power source voltage and the ambient temperature, and to automatically correct for error factors such as production deviations. Therefore, it is necessary to allow for a margin in the variable range to automatically correct the output of loop filter 26, but since the variable range of DC voltage component V.sub.D is limited to the neighborhood of V.sub.DD /2, temperature compensation and correction of errors due to production deviations, etc., are not sufficient.
In view of these problems, the invention is intended to offer a voltage-controlled oscillator and phase-locked loop capable of locking the oscillation frequency by changing the reference clock to accommodate large changes in the data transfer rate.